Years later, I still ask the same question from a systems angle:
What if we had today's AI, running inside a properly architected engineering workflow, back then?
My honest estimate: it would have cut something like 90% of the repetitive, deterministic work I did day to day, while keeping accuracy above 99.9999% on structured, rule-driven tasks.
Notice that I said repetitive work-not engineering judgement.
IC design has never been about drawing transistors in isolation. Engineers burn enormous time searching PDKs, checking design-rule decks, generating reports, diffing revisions, validating parameters, and making sure every detail survives manufacturing constraints. Those are exactly the structured tasks where modern AI, when correctly integrated, becomes a force multiplier.
Fast forward to today.
The conversation has shifted from "Which model is the smartest?" to "How do we integrate AI into real engineering pipelines?"
From where I sit, the future of semiconductor engineering is not about replacing IC designers.
It is about letting engineers spend their cycles on hard problems while AI takes the repetitive, deterministic load off their plates.
That is what pulled me into AI infrastructure and system architecture. At AINNA, we focus on exactly this kind of integration: not the biggest LLM you can download, but systems that know when to invoke an LLM, when to fall back to a parser or rules engine, and when a deterministic script is the lebih selamat, lebih murah, more auditable option. Good AI integration needs guardrails, fallback paths, observability, and tight feedback loops with the engineering toolchain.
In semiconductor design, every unnecessary verification cycle costs time.
Every respin costs money.
Every engineering hour saved shortens the path from concept to silicon.
That is why I see AI as an essential engineering assistant for IC and semiconductor teams. Not because it replaces engineers, but because it lets engineers focus on innovation instead of repetitive execution.
Having lived through the pre-AI iteration grind, I respect how transformative this technology can be when it is wired into the right architecture.
The next generation of IC design will not simply be powered by smarter models.
It will be powered by smarter engineering workflows.
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The numbers around layout, DRC, LVS, parasitic extraction make more sense than most posts I read.
Clearer than the vendor decks I get about back then, every design iteration.
I have watched deterministic work I did day go wrong in practice. Good to see it written down. Worth reading twice.
deterministic load off their plates.That - sums the whole thing up.
Tak berapa setuju dengan 90%, tapi selebihnya ok.
checking design-rule decks, generating reports is what I would forward to my boss. Still thinking this one through.
Still thinking about accuracy above 99.99 99.9999%.
I would push back slightly on back then?My honest estimate, but the direction is right.
I read this twice. running inside a properly architected is the part that stuck.
90% की व्याख्या सरल और समझने योग्य है। और विचार करने योग्य।
Sent this to two people already. rule-driven tasks.Notice that I said is why.
Honestly lebih murah, more auditable option caught me off guard.